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1 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com primary applications product description key features measured performance 77 ghz down converting iq mixer ? automotive radar ? rf & lo frequency range: 75 - 82 ghz ? if frequency range: dc - 100 mhz ? conversion loss: 12 db @ 77ghz ? rf-lo isolation: 18 db @ 77 ghz ? bias: vb = 1.1 v ? technology: hbt with front-side cu/sn pillars ? chip dimensions: 2.46 x 1.89 x 0.38 mm the triquint TGC4702-FC is a down converting iq mixer designed to cover the automotive radar frequency band. the TGC4702-FC typically provides 12 db conversion loss from 75 ? 82 ghz to an if frequency band of dc ? 100 mhz. the tgc4702- fc is designed using triquint?s proven hbt process and front-side cu / sn pillar technology for simplified assembly and low interconnect inductance. die reliability is enhanced by using triquint?s sin passivation process. lead-free and rohs compliant. bias conditions: vb = 1.1 v loin = +11 dbm 10 11 12 13 14 15 16 17 18 19 20 75 76 77 78 79 80 81 82 lo frequency (ghz) rf-lo isolation (db) if out (i), lo - rf = 50 mhz , rfin = -1 dbm, loin = +11 dbm 10.0 10.5 11.0 11.5 12.0 12.5 13.0 75 76 77 78 79 80 81 82 rf frequency (ghz) conversion loss (db)
2 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table ii recommended operating conditions table i absolute maximum ratings 1 / 1 / these ratings represent the maximum operable val ues for this device. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device and / or affect device lifetime. these are stress ratings only, an d functional operation of the device at these conditions is not implied. 2 / combinations of supply voltage, supply current, in put power, and output power shall not exceed the maximum power dissipation listed in table iv. 1 / see assembly diagram for bias instructions. symbol parameter value notes vb bias voltage 2 v 2 / ib bias current 15 ma 2 / pin input continuous wave power (rf + lo) 24 dbm 2 / symbol parameter 1 / value vb bias voltage 1.1 v ib quiescent bias current ~ 1 ma p lo lo input power +11dbm
3 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table iii rf characterization table bias: ib=6ma, f lo =76.55ghz, f rf =76.50 ghz, p lo =11 dbm parameter nominal maximum units conversion loss 12 16 db rf ? lo output isolation 16 db i-q phase 90 degrees
4 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com table iv power dissipation and thermal properties parameter test conditions value notes maximum power dissipation tbaseplate = 85 c pd = 0. 25 w 1 / mounting temperature refer to solder reflow profiles (pg 13) storage temperature -65 to 150 c 1/ channel operating temperature will directly affec t the device median time to failure (mttf). for maximum life, it is recommended that channel temper atures be maintained at the lowest possible levels.
5 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com bias conditions: vb = 1.1 v measured data on flipped die on carrier board if out (i), lo - rf = 50 mhz , rfin = -1 dbm, loin = +11 dbm 10.0 10.5 11.0 11.5 12.0 12.5 13.0 75 76 77 78 79 80 81 82 rf frequency (ghz) conversion loss (db) if out (i), lo - rf = 50 mhz, rfin = -1 dbm @ 77ghz 12 13 14 15 16 17 18 19 0 1 2 3 4 5 6 7 8 9 10 11 12 lo power (dbm) conversion loss (db)
6 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com if out (i), lo - rf = 50 mhz, loin = +11 dbm @ 77.0 5 ghz 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 rf power (dbm) conversion loss (db) bias conditions: vb = 1.1 v measured data on flipped die on carrier board lo - rf = 50 mhz, rfin = -1 dbm, loin = +11 dbm 0 10 20 30 40 50 60 70 80 90 100 74 75 76 77 78 79 80 81 82 83 rf frequency (ghz) i-q phase (degrees)
7 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com bias conditions: vb = 1.1 v measured data on flipped die on carrier board lo - rf = 50 mhz, rfin = -1 dbm @ 77 ghz 0 10 20 30 40 50 60 70 80 90 100 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 lo power (dbm) i-q phase (degrees) lo - rf = 50 mhz, loin = +11 dbm @ 77.05 ghz 0 10 20 30 40 50 60 70 80 90 100 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 rf power (dbm) i-q phase (degrees)
8 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com bias conditions: vb = 1.1 v measured data on flipped die on carrier board loin = +11 dbm 10 11 12 13 14 15 16 17 18 19 20 75 76 77 78 79 80 81 82 lo frequency (ghz) rf-lo isolation (db) loin = 7.5 dbm 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 75 76 77 78 79 80 81 82 83 84 85 rf frequency (ghz) lo-if isolation (db)
9 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com bias conditions: vb = 1.1 v measured data on flipped die on carrier board if out (i), lo - rf = 50 mhz, rfin = -1 dbm, loin = +11 dbm 0 1 2 3 4 5 6 7 8 9 74 75 76 77 78 79 80 81 82 83 rf frequency (ghz) current (ma) if out (i), lo - rf = 50 mhz rfin = -1 dbm @ 77 ghz 0 1 2 3 4 5 6 7 8 9 0 2 4 6 8 10 12 lo power (dbm) current (ma)
10 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com electrical schematic bias procedures bias-up procedure bias-down procedure vb set to 0 v turn off signals adjust vb slowly for 1.1 v (ib will be ~ 1 ma) turn vb to 0 v apply signals to rf in and lo in if out (i) if out (q) TGC4702-FC rf in vb lo in 17 2 12 7 5 or 9
11 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. mechanical drawing drawing is for chip face-up units: millimeters thickness: 0.380 die x,y size tolerance: +/- 0.050 chip edge to pillar dimensions are shown to center of pillar pillar #1,3,6,8,10, 11,13,16,18 rf cpw ground 0.075 ? pillar #2 if out (i) 0.075 ? pillar #4, 10 dc ground 0.075 ? pillar #5, 9 vb 0.075 ? pillar #7 lo in 0.075 ? pillar #12 if out (q) 0.075 ? pillar #17 rf in 0.075 ? pillar #14, 15, 19, 20, 21 mech. support only 0.075 ? 0.000 0.178 0.404 0.628 1.644 1.890 0.000 0.197 0.470 0.698 1.004 1.228 1.454 1.762 1.990 2.263 2.460 1.769 0.492 0.795 1.021 1.245 1.580 2.030 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 0.121 0.121 0.122 0.123 0.123 0.195 2.265 0.197 0.195 1.769 1.771 0.178 0.404 0.628 1.644
12 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. recommended assembly diagram die is flip-chip soldered to a 15 mil thick alumina test substrate TGC4702-FC die (flip-chip bonded) rfin loin ifout (i) vb +1.1v 1 uf ifout (q) 10 nf 10 nf vg can be biased from either pillar # 5 or #9 TGC4702-FC data represented in this datasheet was taken using co-planar waveguide (cpw) transition on the substrate and ground-signal-ground probes
13 TGC4702-FC november 2009 ? rev b triquint semiconductor: www. triquint.com (972)994 -8465 fax (972)994-8504 info-mmw@tqs.com gaas mmic devices are susceptible to damage from el ectrostatic discharge. proper precautions should be observed during handling, assembly and test. assembly notes ordering information part package style TGC4702-FC gaas mmic die typical reflow profiles for triquint cu / sn pillars component placement and die attach assembly notes: ? vacuum pencils and/or vacuum collets are the prefe rred method of pick up. ? air bridges must be avoided during placement. ? cu pillars on die are 65 um tall with a 22 um tall sn solder cap. ? recommended board metallization is evaporated tiw f ollowed by nickel/gold at pillar attach interface. ni is the adhesion layer for the solder and the gold keeps the ni from oxidizing . the au should be kept to a minimum to avoid embri ttlement; suggested au / sn mass ratio must not exceed 8%. ? au metallization is not recommended on traces due to solder wicking and consumption concerns. if au traces are used, a physical solder barrier must be applied or designed into the pad area of the board. the barrier must be suffici ent to keep the solder from undercutting the barrier. reflow process assembly notes: ? minimum alloying temperatures 245 0 c. ? repeating reflow cycles is not recommended due to sn consumption on the first reflow cycle. ? an alloy station or conveyor furnace with an inert atmosphere such as n2 should be used. ? dip copper pillars in ?no-clean flip chip? flux pri or to solder attach. suggest using a high temperatu re flux. avoid exposing entire die to flux. ? if screen printing flux, use small apertures and m inimize volume of flux applied. ? coefficient of thermal expansion matching between the mmic and the substrate/board is critical for lo ng-term reliability. ? devices must be stored in a dry nitrogen atmospher e. ? suggested reflow will depend on board material and density. process sn reflow ramp-up rate 3 0 c/sec flux activation time and temperature 60 ? 120 sec @ 1 40 ? 160 0 c time above melting point (245 0 c) 60 ? 150 sec max peak temperature 300 0 c time within 5 0 c of peak temperature 10 ? 20 sec ramp-down rate 4 ? 6 0 c/sec

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